1. Field of the Invention
Exemplary embodiments of the present invention relate to a latency control circuit, a latency control method thereof, and a semiconductor memory device including the latency control circuit.
2. Description of the Related Art
Semiconductor devices inside of a system operate by exchanging signals and data with each other. For example, a semiconductor memory device, such as Dynamic Random Access Memory (DRAM) device, outputs a stored data and transfers the data to a controller of the system, after the controller applies a read command to the semiconductor memory device. However, the semiconductor memory device cannot output the data instantly at the moment when the semiconductor memory device receives the read command because it takes some time to call the data out of the semiconductor memory device and output the data through an array process.
In order to implement semiconductor devices, it is desirable to define the waiting time from the moment when a particular signal is applied to a semiconductor device to the moment when an operation corresponding to the signal. This defined time is called latency. For example, the time taken from the moment when a read command is applied to a DRAM device to the moment when a data is actually outputted from the DRAM device is referred to as CAS latency (CL). If the CAS latency is 5 clock cycles (1 tCK=one clock cycle), a corresponding data should be outputted through a DQ pad of the DRAM device exactly 5 clock cycles after a read command is applied to an input pad of the DRAM device. A latency control circuit functions to control a delay amount of an input signal so that an operation, corresponding to a signal applied to a semiconductor device, can be performed at an exact timing in compliance with the latency of the signal.
A latency control circuit is generally used along with a Delay Locked Loop (DLL). A delay locked loop is a circuit for synchronizing a clock used in a system and a semiconductor device. For example, a semiconductor device, such as Double Data Rate Synchronous DRAM (DDR SDRAM) device, may transfer diverse signals and data by using an internal clock having the same frequency as the frequency of an external clock used in an external system. Herein, the clock inputted to the semiconductor device is applied at first in the state that the clock is synchronized with the external clock, but the clock is delayed as it passes through several constituent elements inside the semiconductor device, and therefore, the clock may not be synchronized with the external clock by the time the clock is outputted to the outside. Therefore, for stable transfer of a signal and a data, the internal clock should be reversely compensated for the delay amount caused in a signal transfer path. For this purpose a delay locked loop (DLL) is used such that the outputted internal clock and the external clock are synchronized in an external system.
FIG. 1 is a block view of a known semiconductor device including a latency control circuit.
Referring to FIG. 1, the known semiconductor device includes a latency control unit 101, a latency delay unit 103, and a delay locked loop unit 105.
The delay locked loop unit 105 generates an internal clock DLLCLK by delaying an external clock EXTCLK inputted to the semiconductor device. The delay amount of the delay locked loop unit 105 is controlled to make the internal clock DLLCLK have the same phase as the external clock EXTCLK when the internal clock DLLCLK is outputted to the outside through an internal path of the semiconductor device.
The latency control unit 101 decides a latency delay amount LSHIFT by using the external clock EXTCLK and the internal clock DLLCLK when a delay amount reset signal OERST is enabled. For example, when it is assumed that the latency between an input signal INPUT and an A operation in a target circuit (not shown) corresponding to the input signal INPUT is N clock cycles (N tCK), the target circuit performs the A operation in N clock cycles from the moment when the input signal INPUT is applied to the semiconductor device based on the external clock EXTCLK. Therefore, the input signal INPUT should arrive at the target circuit at an exact timing in compliance with the latency, and the latency control unit 101 controls the latency delay amount LSHIFT to delay the input signal INPUT as much as the given latency.
FIG. 2 is a timing diagram illustrating the operation of the latency delay unit 103. When it is assumed that the latency delay amount LSHIFT decided in the latency control unit 101 is two clock cycles (2 tCK), as illustrated in FIG. 2, the latency delay unit 103 generates a latency signal LATC by delaying the input signal INPUT synchronized with the external clock EXTCLK for two clock cycles based on the external clock EXTCLK and synchronizing the delayed input signal with the internal clock DLLCLK. Herein, the operation of synchronizing a signal with different clocks is referred to as domain crossing. The internal clock DLLCLK is generated to have the same phase as the phase of the external clock EXTCLK at the moment when the internal clock DLLCLK arrives at the target circuit. Therefore, the latency signal LATC synchronized with the internal clock DLLCLK can arrive at the target circuit at the exact moment in compliance with the latency based on the external clock EXTCLK.
In the known latency control circuit, however, diverse variables may occur in the delay path of the input signal INPUT according to variation in the process, voltage, and/or temperature (PVT) conditions of the semiconductor device. In particular, when the phase of the external clock EXTCLK and the phase of the internal clock DLLCLK slightly differ from each other, the possibility for failure occurring in the domain crossing is increased. FIGS. 3A and 3B illustrate this concern.
FIG. 3A is an operation timing diagram of the latency delay unit 103 when the phase of the external clock EXTCLK is slightly ahead of the phase of the internal clock DLLCLK.
Referring to FIG. 3A, when the input signal INPUT is delayed more than the latency delay amount LSHIFT due to a change in the PVT conditions of the semiconductor device, a delayed input signal INPUT_DL is synchronized with the internal clock DLLCLK at a moment one clock cycle behind the moment it is supposed to be synchronized in the normal case (i.e., where a pass occurs). Therefore, a failure occurs because the latency signal LATC is enabled one clock cycle later than the given latency.
FIG. 3B is an operation timing diagram of the latency delay unit 103 when the phase of the internal clock DLLCLK is slightly ahead of the phase of the external clock EXTCLK.
Referring to FIG. 3B, when the input signal INPUT is delayed less than the latency delay amount LSHIFT due to a change in the PVT conditions of the semiconductor device, the delayed input signal INPUT_DL is synchronized with the internal clock DLLCLK at a moment one clock cycle earlier than the moment it is supposed to be synchronized in the normal case (i.e., where a pass occurs). Therefore, a failure occurs because the latency signal LATC is enabled one clock cycle faster than the given latency.